VSD – Library characterization and modelling – Part 1

VLSI - The heart of STA, PNR, CTS and Crosstalk

Created by: Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)

What Will I Learn?

• Understand timing, noise and power libraries syntax and semantics
• Develop models for logic gates and macros
• Use the above generated models and do STA

Requirements

• Full knowledge on circuit design and SPICE simulations
• Full knowledge on custom layout
• Nice to have knowledge on Physical design, Static timing analysis, Noise & Crosstalk and Clock tree synthesis
• You can refer to my existing courses or any other external material, but knowledge about above all is a must

Target audience

• Research professionals
• Graduate students
• Circuit and PDK designers
• Characterization engineers
• CAD developers
• Managers, Mentors and the merely curious