VSD – Pipelining RISC-V with Transaction-Level Verilog
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VSD – Pipelining RISC-V with Transaction-Level Verilog
$34.99
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VSD - Pipelining RISC-V with Transaction-Level Verilog
★★★★★
$479.00 in stock
Udemy.com
as of March 15, 2026 5:35 pm
Front end VLSI design can’t get easier than this
Created by:
Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Digital and Sign-off expert at VLSI System Design(VSD)
Created by:
Steven Hoover
Founder, Redwood EDA
Founder, Redwood EDA
Rating:4.14 (89reviews)
744students enrolled
What Will I Learn?
- Students will be able to use and implement concepts of pipelining using TL-verilog language and Makerchip platform
- Build their own verilog models for IP's using a simpler and powerful Verilog design environment
Requirements
- You should know basics of digital design like flip-flops, gates, clock, etc.
- You should have finished RISC-V ISA - Part 1a course on Udemy if new to CPU microarchitecture
- You should have a modern web browser like chrome, and login to Makerchip to ensure compatibility
Target audience
- Anyone who wants to learn transaction-level verilog
- Anyone who wants to stay ahead of curve in frontend VLSI
- Anyone who wants to learn and implement pipelining concepts in field of computer architecture
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