Verilog HDL Fundamentals for Digital Design and Verification

Build a strong Verilog language foundation by implementing combinational / sequential digital circuits and testbenches

Created by: Ovidiu Plugariu
Digital Design and Functional Verification Engineer, Ph.D

What Will I Learn?

• Master the basics of Verilog language for designing synthesizable digital circuits for ASIC / FPGA
• Differentiate between Verilog structural / dataflow / behavioral design styles and how / when to use them in Digital Design and Verification
• Implement combinational and sequential digital circuits using Verilog HDL starting from schematics or functional specifications
• Create and simulate a Verilog testbench for a digital circuit starting from its functional specifications
• Examine the behavior of a digital circuit receiving stimulus in a testbench, using an industry-level simulator (free for academic purposes)
• Explicit visual explanations for the 80+ downloadable code examples, circuits, and testbenches offering you increased retention and accelerated learning

Requirements

• Basic notions of programming languages (like C / C++/ Python)
• Interest in hardware description languages. You will learn everything about Verilog HDL for Design and Verification in this course
• Interest in digital microelectronics, digital circuits design and verification

Target audience

• Computer Science, Electronics, Telecommunications, and Microelectronics students who want to learn Verilog for their projects and faculty assignments
• Electronics and Microelectronics hobbyists who want to learn the Verilog Hardware Description Language
• Beginners who aspire to a career as a Digital Design Engineer or a Functional Verification Engineer
• Beginners in digital microelectronics and digital circuits design curious about the Verilog Hardware Description language