Hands-On ZYNQ: Mastering AXI4 Bus Protocol
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Hands-On ZYNQ: Mastering AXI4 Bus Protocol
★★★★★
$10.00 in stock
Udemy.com
as of January 9, 2026 9:27 pm
Create Verilog and C codes for implementing the AXI4 bus protocol on ZYNQ FPGA
Created by:
Erwin Ouyang
FPGA Engineer, 10000+ Students
FPGA Engineer, 10000+ Students
Rating:4.23 (165reviews)
1428students enrolled
What Will I Learn?
- Use Xilinx AXI4-based IP Cores
- Create your own AXI4-based IP Cores from scratch
- Create an AXI4-based Hardware Accelerator IP Core (GCD case study)
- Create an AXI4-based Transceiver IP Core (UART case study)
Requirements
- Basics of Digital Systems
- HDL (Verilog) and C/C++ programming experience
- Vivado WebPACK (free) Edition 2016.04 (recommended) or higher
- A ZYBO development board (or other ZYNQ boards)
Target audience
- Students or engineers who are working in Embedded or SoC design
- Students or engineers who have a knowledge of HDL (Verilog) and C/C++ but new to AXI4 bus protocol
- Students or engineers who are already using ZYNQ and want to create your own IP cores with AXI4 bus protocol
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