Verification Series Part 7:SystemVerilog Functional Coverage

Step by Step Guide from Scratch

Created by: Kumar Khandagle
Trainer @ NAMASTE FPGA

What Will I Learn?

• Usage of Functional Coverage in Verification
• Implicit and Explicit Bins, Default bins
• Illegal bins, Ignore bins, WIldcard bins Default bins
• Covergroup, Sampling events, Reusable Covergroup
• Transition bins and Cross Coverage
• Usage of Functional Coverage in Verilog and SystemVerilog TB
• Demonstrations of Functional Coverage with Counters, Priority Encoders, Adders, FIFO, SPI and few other RTL's

Requirements

• Fundamentals of Verilog, Digital Electronics, SystemVerilog

Target audience

• Anyone interested in adopting Functional Coverage in the Verification process to generate Stimulus meeting Verification plans