Complete Verilog HDL programming with Examples and Projects

Fundamentals, Design flow, modeling levels, Datatypes, test bench, Tasks & system tasks, FSM, FPGA & examples & Projects

Created by: Surender Reddy T
Developer

What Will I Learn?

• Learning Verilog HDL Programming fundamental concepts and properties compare to C Language, feature & advantages of Verilog HDL over VHDL
• VLSI Design flow ( FPGA & ASIC) and Difference between FPGA vs ASIC
• Different design methodologies in Verilog HDL programming with examples
• Behavioral modeling with blocking & Non-Blocking concepts and real time examples
• Test bench Verilog program with examples
• Task & system tasks with examples for random data generator, file based operations and memory load operations, and file representation input & output etc.
• Finite state machine (FSM) with example for both Mealy & Moore and Sequence detector FSM
• Complete design & test bench programming for Memory controllers
• Complete design & test bench programming for FIFO controller
• Complete design & test bench programming for Encoder & decoder for Hamming code Error detection correction
• Basics of FPGA

Requirements

• Intension to learn
• basic in C Language
• basics in Digital design ( not compulsory)

Target audience

• Undergraduate Electronics and computer science engineering students
• Graduate students who planning their career in VLSI domain front end (Design & verification)
• Advanced under graduate students, who willing to do project in front end VLSI design