VSD – Static Timing Analysis – II
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VSD – Static Timing Analysis – II
Original price was: $49.99.$10.00Current price is: $10.00.
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VSD - Static Timing Analysis - II
★★★★★
$49.99
in stock
Udemy.com
as of January 17, 2026 9:54 pm
VLSI - Analyse your chip timing for free
Created by:
Kunal Ghosh
Digital and Sign-off expert at VLSI System Design(VSD)
Digital and Sign-off expert at VLSI System Design(VSD)
Rating:4.17 (750reviews)
5252students enrolled
What Will I Learn?
- Students will be able to do a real full chip static timing analysis with $0 spent, as designs and tools used in this course are opensource
- Students will be able to appreciate power of opensource EDA tools, like Opentimer used in this course, and help in contributing towards the development
- Students can explore commercial tools with knowledge and concepts from this course, quite easily
- Manage a entire chip timing signoff
Requirements
- Static Timing analysis - part 1 course needs to be fully completed to start this course. No exceptions
- Knowledge of physical design flow and clock tree synthesis will be helpful
Target audience
- Anyone who has completed static timing analysis - part 1 course
- Anyone (with 100% static timing analysis - part 1 course completed) who has basic knowledge on flipflops, gates and digital logic
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